1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device.
2. Description of the Related Art
As the integration degree of a non-volatile memory device, such as a flash memory device, increases, additional costs and time are spent in testing a non-volatile memory device.
An exemplary operation of programming a test data in a memory cell (not shown) during a test operation of a non-volatile memory device is performed as follows. For illustration purposes, it is assumed that a non-volatile memory device includes N page buffers and N bit lines.
Each of the N page buffers receives and stores a test data that is inputted from an external device. The test data stored in the respective N page buffers are loaded onto N bit lines, respectively, and programmed in N memory cells that are coupled with the N bit lines. When a test operation is performed in the general program operation, the test data is inputted from an external device and thus, the test operation takes additional time.
To reduce the test time, the process of receiving a test data from an external device may be obviated, by generating a test data internally and storing the test data in a page buffer. This method will be described in detail with reference to FIG. 1.
FIG. 1 illustrates a conventional non-volatile memory device. The non-volatile memory device may include N bit lines BL1 to BLN, N page buffers 10_1 to 10_N, and N data controllers 20_1 to 20_N.
Each of the N page buffers 10_1 to 10_N stores a write data, which means a data to be programmed in a memory cell (not shown).
Each of the N data controllers 20_1 to 20_N corresponds to the N page buffers 10_1 to 10_N, respectively. When a reset signal RST is activated, each of the N data controllers 20_1 to 20_N controls the corresponding page buffer to store the write data of a logic high level. When a set signal SET is activated, each of the N data controllers 20_1 to 20_N controls the corresponding page buffer to store the write data of a logic low level.
During the test operation of the non-volatile memory device illustrated in FIG. 1, an operation of generating write data of a pattern and programming the write data in memory cells (not shown) is performed as follows.
The reset signal RST is enabled to a logic high level in the initial duration of the test operation. Each of the N data controllers 20_1 to 20_N controls the corresponding page buffer to store the write data of a logic high level in response to the reset signal RST of a logic high level. As a result, a high level write data is loaded on the latch node QC of each of the N page buffers 10_1 to 10_N. The write data loaded on the latch node QC of each of the N page buffers 10_1 to 10_N is applied to a memory cell (not shown) through a bit line. According to an example, a data of ‘11111111 . . . ’ is programmed in N memory cells (not shown).
Meanwhile, when the set signal SET is enabled to a logic high level in the initial duration of the test operation, a write data of a logic low level is loaded on the latch node QC of each of the N page buffers 10_1 to 10_N. According to an example, a data of ‘00000000. . . ’ is programmed in N memory cells (not shown).
However, when the test operation is performed as described above, the pattern of the test data that are programmed in memory cells (not shown) is limited to ‘11111111. . . ’ or ‘00000000 . . . ’.